1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining critical dimension variation in a line structure.
2. Description of the related art
Semiconductor integrated circuit devices are employed in numerous applications, including microprocessors. Generally, the performance of a semiconductor device is dependent on both the density and the speed of the devices formed therein. A common element of a semiconductor device that has a great impact on its performance is a transistor. Design features, such as gate length and channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as microprocessors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.
A transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 xcexcm, whereas the distance of the drain and source, i.e., the gate length, may be reduced down to 0.2 xcexcm or less. As the gate length of the channel has been reduced to obtain the desired switching characteristic of the source-drain line, the length of the gate electrode is also reduced. Since the gate electrode is typically contacted at one end of its structure, the electrical charges have to be transported along the entire width of the gate electrode, i.e., up to 20 xcexcm, to uniformly build up the transverse electric field that is necessary for forming the channel between the source and drain regions. Due to the small length of the gate electrode, which usually consists of polycrystalline silicon, the electrical resistance of the gate electrode is relatively high, and it may cause high RC-delay time constants. Hence, the transverse electrical field necessary for fully opening the channel is delayed, thereby further deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased, and the operating frequency, i.e., the clock frequency, may be adversely affected.
Transistors are formed through a series of steps. An exemplary transistor structure 100 is described in reference to FIGS. 1A and 1B. Initially, shallow trench isolation regions 105 are formed in a substrate 110 by etching trenches into the substrate 110 and, thereafter, filling the trenches with an appropriate insulating material (e.g., silicon dioxide). Next, a gate insulation layer 115 is formed over the substrate 110 between the trench isolation regions 105. This gate insulation layer 115 may be comprised of a variety of materials, but it is typically comprised of a thermally grown layer of silicon dioxide. Thereafter, a polysilicon gate electrode layer 120 is formed above the gate insulation layer 115. An antireflective coating (ARC) layer 125 may be formed over the polysilicon layer 120 to minimize notches caused by reflections during subsequent photolithographic techniques. A photoresist layer 130 is formed over the ARC layer 125 and patterned to form a mask for etching gate electrodes 135 as seen in FIG. 1B, a top view of the transistor structure 100 of FIG. 1A. Of course, millions of such gate electrodes 135 may be formed across the entire surface of the substrate 110 during this patterning process.
The gate electrode 135 passes over isolation structures 105 associated with adjacent transistor structures. The isolation structures 105 are typically not flush with respect to the surface of the substrate 11 O. The distance that the isolation structures 105 extend beyond the surface of the substrate 110 may be referred to as the step height, H, of the isolation structures 105. In regions 140 where the photoresist layer 130 passes over the isolation structures 105, its thickness may be reduced due to the step height of the isolation structures 105. When the photoresist layer 130 is subsequently exposed in a stepper to form the mask pattern, the reduced thickness regions 140 receive an effectively higher exposure dose due to the reduced thickness, resulting in a wider pattern in the exposed portions. The exposed portions of the photoresist layer 130 are removed and the remaining portions are used as a pattern for etching the gate electrodes 135. The remaining portions have a narrower pattern in the reduced thickness regions 140. Thus, when the gate electrodes 135 are subsequently etched, they also have narrower portions 145 in the regions overlying the isolation structures 105.
The width variation across the length of the gate electrodes 135 described above may be referred to as a critical dimension (CD) variation. In modem integrated circuit devices, a plurality of gate electrodes 135 may be formed adjacent one another, separated by a defined pitch. CD variation effectively reduces the width of the gate electrodes 135. A subsequently formed interlayer dielectric (ILD) layer (not shown) is formed over the transistor structures 100 and between the gate electrodes 135 to insulate them from one another. Device designers must take into account the potential magnitude of the CD variation in designing the layout of the transistors 100 to ensure the insulating ability of the ILD layer and the conductive ability of the gate electrodes 135.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for determining critical dimension variation. The method includes providing a wafer having a grating structure comprising a plurality of lines; illuminating at least a portion of the lines with a light source; measuring light reflected from the illuminated portion of the lines to generate a reflection profile; and determining a critical dimension variation measurement of the lines based on the reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to receive a wafer having a grating structure comprising a plurality of lines. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the lines. The detector is adapted to measure light reflected from the illuminated portion of the lines to generate a reflection profile. The data processing unit is adapted to determine a critical dimension variation measurement of the lines based on the reflection profile.